1. Field of the Invention
The present invention relates to a chip stack package, and more particularly, to a chip stack package having a DNA-like interconnection structure between the packaged chips. The DNA-like interconnection structure comprises spiral, electrical interconnection strands constructed by metal layers in or on each chip and the through silicon vias (TSVs) for the connection between chips.
2. Description of the Prior Art
Packaging technologies for a semiconductor integrated device have been continuously developed to satisfy the demands for miniaturization and mounting efficiency. As the miniaturization and high performance are required in the recent development trends of the electronic appliance, various semiconductor stacking technologies have been developed. When applying the stack technology in the field of memory devices, it is possible to realize a packaged product having the memory capacity more than two times the memory capacity of an unpackaged chip, and thus it is possible to increase the efficiency of the mounting area usage.
In the recent years, a chip stack package having through silicon via (TSV) structure has been proposed due to its convenient property for connecting chips. FIG. 1 illustrates a conventional chip stack package having TSVs. As shown in FIG. 1, briefly, a TSV 102 is formed by forming a hole in each chip 104 and filling the hole with conductive material. The TSVs 102a, 102b, 102c, 102d create a short electrical connection path between the chips 104a, 104b, 104c, and 104d. Compared with conventional wire bonding packages, there is no need to further include additional areas on the substrate for wire bonding, thus both the size and the height of the chip stack package 100 can be reduced.
However, the selection between the chips 104 in the prior art chip stack package 100 is problematic. For example, if one wants to select the chip 104a to drive the chip 104a to be operated by an input/output signal in the subsequent step, an individual chip selection signal is required and should be transmitted to the chip 104a in the beginning. However, since the TSVs 102a, 102b, 102c, 102d are all connected together, there is no independent route specific for the chip 104a. When the substrate 106 provides a chip selection signal to the TSV 102a, 102b, 102c, 102d, all the chips 104a, 104b, 104c, 104d would receive the same signal. Therefore, it is difficult to select the chip 104a by using the TSVs 102 in the conventional chip stack package 100. Some researchers have overcome the problem by marking an individual ID on each chip 102 during the wafer stage so as to enable the chip selection function. However, this method is relatively complex, time-consuming and thus not economical. In light of the above, there is still a need to have a chip stack package capable of transmitting chip selection signals independently, without the need of marking an individual ID on each chip during the wafer stage.